/***********************************************************************************************************************
*                                                                                                                      *
* SPLASH build system v0.1                                                                                             *
*                                                                                                                      *
* Copyright (c) 2013 Andrew D. Zonenberg                                                                               *
* All rights reserved.                                                                                                 *
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* following conditions are met:                                                                                        *
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*      following disclaimer.                                                                                           *
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*    * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the       *
*      following disclaimer in the documentation and/or other materials provided with the distribution.                *
*                                                                                                                      *
*    * Neither the name of the author nor the names of any contributors may be used to endorse or promote products     *
*      derived from this software without specific prior written permission.                                           *
*                                                                                                                      *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   *
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* POSSIBILITY OF SUCH DAMAGE.                                                                                          *
*                                                                                                                      *
***********************************************************************************************************************/

#include "splashcore.h"

using namespace std;

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGASynthesisHierarchyFlag

FPGASynthesisHierarchyFlag::FPGASynthesisHierarchyFlag(FPGASynthesisHierarchyFlag::HierarchyMode mode)
	: m_mode(mode)
{
	
}

FPGASynthesisHierarchyFlag::~FPGASynthesisHierarchyFlag()
{

}

FPGASynthesisFlag* FPGASynthesisHierarchyFlag::Clone() const
{
	return new FPGASynthesisHierarchyFlag(m_mode);
}

string FPGASynthesisHierarchyFlag::toString(const FPGAToolchain* toolchain)
{
	if(dynamic_cast<const XilinxFPGAToolchain*>(toolchain) != NULL)
	{
		switch(m_mode)
		{
		case HIERARCHY_NONE:
			return "-keep_hierarchy no\n";
		case HIERARCHY_SOFT:
			return "-keep_hierarchy soft\n";
		case HIERARCHY_KEEP:
			return "-keep_hierarchy yes\n";
		default:
			FatalError("FPGASynthesisHierarchyFlag: unknown value\n");
		}
	}
	else
		FatalError("FPGASynthesisHierarchyFlag is not supported on this toolchain yet\n");
}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGANetlistHierarchyFlag

FPGANetlistHierarchyFlag::FPGANetlistHierarchyFlag(FPGANetlistHierarchyFlag::HierarchyMode mode)
	: m_mode(mode)
{
	
}

FPGANetlistHierarchyFlag::~FPGANetlistHierarchyFlag()
{

}

FPGASynthesisFlag* FPGANetlistHierarchyFlag::Clone() const
{
	return new FPGANetlistHierarchyFlag(m_mode);
}

string FPGANetlistHierarchyFlag::toString(const FPGAToolchain* toolchain)
{
	if(dynamic_cast<const XilinxFPGAToolchain*>(toolchain) != NULL)
	{
		switch(m_mode)
		{
		case HIERARCHY_AS_OPTIMIZED:
			return "-netlist_hierarchy as_optimized\n";
		case HIERARCHY_REBUILT:
			return "-netlist_hierarchy rebuilt\n";
		default:
			FatalError("FPGANetlistHierarchyFlag: unknown value\n");
		}
	}
	else
		FatalError("FPGANetlistHierarchyFlag is not supported on this toolchain yet\n");
}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGASynthesisOptimizationFlag

FPGASynthesisOptimizationFlag::FPGASynthesisOptimizationFlag(
	FPGASynthesisOptimizationFlag::OptimizationLevel mode,
	FPGASynthesisOptimizationFlag::OptimizationGoal goal)
	: m_mode(mode)
	, m_goal(goal)
{
	
}

FPGASynthesisOptimizationFlag::~FPGASynthesisOptimizationFlag()
{

}

FPGASynthesisFlag* FPGASynthesisOptimizationFlag::Clone() const
{
	return new FPGASynthesisOptimizationFlag(m_mode, m_goal);
}

string FPGASynthesisOptimizationFlag::toString(const FPGAToolchain* toolchain)
{
	if(dynamic_cast<const XilinxFPGAToolchain*>(toolchain) != NULL)
	{
		string level;
		string goal;
		
		//Level
		switch(m_mode)
		{
		case OPT_NONE:
			level = "-opt_level 0\n";
			break;
		case OPT_NORMAL:
			level = "-opt_level 1\n";
			break;
		case OPT_HIGH:
			level = "-opt_level 2\n";
			break;
		default:
			FatalError("FPGASynthesisOptimizationFlag: unknown value\n");
		}
		
		//Goal
		switch(m_goal)
		{
		case OPT_SPEED:
			goal = "-opt_mode speed\n";
			break;
		case OPT_AREA:
			goal = "-opt_mode area\n";
			break;
		default:
			FatalError("FPGASynthesisOptimizationFlag: unknown value\n");
		}
		
		return level + goal;
	}
	else
		FatalError("FPGASynthesisOptimizationFlag is not supported on this toolchain yet\n");
}

////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGASynthesisMacroFlag

FPGASynthesisMacroFlag::FPGASynthesisMacroFlag(std::string name, std::string value)
	: m_name(name)
	, m_value(value)
{
	
}

FPGASynthesisMacroFlag::~FPGASynthesisMacroFlag()
{

}

FPGASynthesisFlag* FPGASynthesisMacroFlag::Clone() const
{
	return new FPGASynthesisMacroFlag(m_name, m_value);
}

string FPGASynthesisMacroFlag::toString(const FPGAToolchain* toolchain)
{
	if(dynamic_cast<const YosysCrowbarFPGAToolchain*>(toolchain) != NULL)
	{
		//handled during read_verilog specially, so nothing elsewhere
		return "";
	}
	else
		FatalError("FPGASynthesisMacroFlag is not supported on this toolchain yet\n");
}
